Along with the explosion of cloud business, the scale of single cloud data center campus of large Internet companies has rapidly increased from 100,000 to 300,000 spaces. For the increasing demand of 100G data center network clusters, 100G switches with higher access density need to be developed. Large capacity single chip is simple to develop and easy to use. It has always been the first choice of self-developed switch ASIC chip. A 128*100G switch form factor based on the 12.8T chip and up to 256*100G switches based on the 25.6T chip that will be mass produced soon are the conventional forms of core switches. However, with the 25.6T chip, for example, a 256*100G switch takes up 8RU of space and requires at least nine high-speed single boards. The backplane design of 8RU Chassis made of single chip is very complicated and the PAM4 alignment is relatively long, so 256*100G Chassis of 8RU is not the optimal choice. Based on this, the 25.6T chip is designed as a 64*400G form factor with 64 pieces 400G ports using a four-in-one FanOut optical module, which can realize 256*100G with low cost and high reliability. This design only occupies 2RU or 4RU space, which greatly reduces the complexity of system design and the cost of the whole machine.
The value of Silicon Photonics 400G DR1/DR4 optical modules
One divided into four Fan-out architecture, requiring the interconnection of optical modules using multiple parallel solutions, and the industry is currently divided into two main multimode and single-mode multi-channel modules. In terms of 400G module architecture and 100G SerDes port rate in the future, compared with multimode, single-mode not only has longer transmission distance, but also has fewer actual optical channels. In the selection of single-mode chip, EML (Externally Modulated Laser ) and SiPh (Silicon Photonics ) have their own advantages. The InP based EML realizes single wave 100G transmission earlier, but the yield and reliability level are low and sensitive to temperature. While SiPh has low cost, good reliability and easy to scale. In this scenario we choose SiPh instead of EML as the chip solution, not only because of the above factors, but also because of longer term considerations.
In terms of scheme, 400G DR4 is the basic form of 400G silicon optical module. 400G DR4 is an optical transceiver module designed for 400G Ethernet data center interconnect in 400G QSFP-DD (Quad Small Form Factor Pluggable-double density ) form factor. On the transmitter end, this DR4 module converts 8 channels of 50Gb/s (PAM4) electrical signal into 4 channels of parallel optical output data, each capable of 100Gb/s data rate for an aggregated bandwidth of 400Gbls. On the receiver side, the optic transceiver converts 4 lanes of parallel optical data of 100Gbp/s each lane for an aggregated of 400Gbp/s to supports 8 lanes of 50Gb/s PAM4 electrical output signal. The 400G QSFP-DD DR4 fiber module achieves the transmission over SMF(single-mode fiber) with an MPO-12 connector. It supports a max transmission distance of 500 meters on 1310nm center wavelength. The product is designed with digital diagnostic functions according to the QSFP-DD Multi-Source Agreement (MSA).
In the 400G era of the data center, 400G DR4 can not only realize the four-in-one Breakout networking, which can be transmitted to 100G DR1/FR1, but also replace the short-range multimode 400G optical module interconnection on the access side, with end-to-end cost competitiveness. With the advantage of single fiber transmission, the packaging with multi wavelength light source can be easily switched to WDM module. At the same time, the optical switching equipment in the data center is evolving towards the form of Co-package, and the multi-channel parallel silicon optical integration scheme will be the standard form.
Silicon Photonics module scheme design and testing
From both performance and resource considerations, we chose two silicon optical solutions, the first highlighting the advanced packaging and overall performance, using an integrated silicon optical engine solution, and the DSP part of the industry’s more advanced 7nm low-power chip. The other scheme highlights the resources and industrial chain, and adopts the silicon optical chip scheme with separate packaging. Some of the silicon optical chips have excellent performance, while the DSP adopts a more mature 16nm chip. Because of the wide temperature photoelectric effect of silicon light, both schemes do not need TEC temperature control. Compared with the traditional EML scheme, they can work normally in a wider temperature range and have more advantages in cost.
Scheme 1
The core chip used in the solution is a 3D package silicon fully integrated optical engine, which integrates MZM, PD, Driver and TIA functions. The 3D BGA package has the advantage of reducing high frequency attenuation and optimizing the modulation balance of the MZM modulator. In addition, the digital signal processing (i.e. DSP chip) uses a 400G 7nm PAM4 (8:4) chip, which is the most advanced in the industry, with a single chip power consumption <4W.
The package requires a special design, so a customized FA package assembly is used to reduce coupling loss and can cover both short- and long-range specifications, i.e. 400G QSFP-DD DR4 (500m) and 400G QSFP-DD DR4+ (2km).
After testing, the indicators of the Silicon Photonics optical module in this scheme exceed the expectation: its received bit error rate is BER < 10-8 when the FEC is not turned on, and the BER floor can achieve 10-10; besides, the TDECQ index of the eye diagram at the transmitting end is generally less than 0.6dB, and can be less than 0.5dB after BER equalization. The measured overall power consumption of this optical module is less than 8.9w, even better than most 400G multimode optical modules, which also benefits from the power consumption optimization of integrated pic and 7nmDSP. However, there is still some room for optimization in this scheme.
Scheme 2
The scheme adopts photoelectric chip separation packaging, that is, the signals between chips are connected through PCB and golden wire. Its packaging form is flexible and its comprehensive yield is high. In addition to DSP, driver and TIA, Seed-Laser，SiP，SiGe-PD，FA and other optical chips are localization schemes with controllable resources. The power consumption of 400G PAM4 (8:4) DSP chip in 16nm process is 5.8W.
In fact, the separated silicon optical chip can make bold attempts in single-chip design with less IO design constraints. The bandwidth of this single chip has far exceeded 100Gbps/lane. At present, the performance can reach 200Gbps/lane, which is equivalent to 800G single module output under the same packaging density. The TEDCQ of the eye diagram of the module body test is <2dB, which can meet the requirements of both short-range and long-range applications. Multichip integration scheme and multichip separation scheme are two basic forms of silicon optical module. The advantages of the integration scheme lie in the balance of high-speed performance, high density and small volume; The advantage of the separation scheme is that the photoelectric chip combination is flexible, the packaging yield is high, and the single chip is easy to be compatible. Therefore, the simultaneous development of two technical solutions for the design of 400G silicon optical modules is more conducive to accelerate the application of future data optical interconnection technology.
